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Tshiab Thawj XC18V04VQG44C Spot Tshuag FPGA Field Programmable Gate Array Logic IC Chip Integrated Circuits

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Product Detail

Khoom cim npe

Yam khoom

HOM Kev piav qhia
Qeb Integrated Circuits (ICs)

Nco

Configuration Proms rau FPGAs

Mfr AMD Xilinx
Series -
Pob Tais
Yam khoom Tsis siv lawm
Hom Programmable Hauv System Programmable
Memory Loj 4 Mb
Voltage - Khoom siv 3V ~ 3.6V
Ua haujlwm kub 0 ° C ~ 70 ° C
Mounting Hom Nto Mount
Pob / Case 44- QWB
Cov Khoom Muag Khoom Pob 44-VQFP (10 × 10)
Base Product Number XC18V04

Cov ntaub ntawv & Media

TSEEM CEEB LINK
Cov ntaub ntawv XC18V00 Series
Environmental Information Xiliinx RoHS Cert

Xilinx REACH211 Cert

PCN Obsolescence/EOL Ntau yam khoom siv 01/Jun/2015

Mult Device EOL Rev3 9/May/2016

Xaus Lub Neej 10/JAN/2022

PCN Part Status Hloov Qhov Chaw Reactivated 25/Apr/2016
HTML Datasheet XC18V00 Series

Environmental & Export Classifications

TXOJ CAI Kev piav qhia
RoHS Status ROHS3 raws
Moisture Sensitivity Level (MSL) 3 (168 teev)
REACH xwm txheej REACH Tsis muaj kev cuam tshuam
ECCN 3a991b 1
HTSUS 8542.32.0071 ib

Cov peev txheej ntxiv

TXOJ CAI Kev piav qhia
Txheem pob 160

Xilinx Memory - Configuration Proms rau FPGAs

Xilinx qhia XC18V00 series ntawm hauv-system programmable configuration PROMs (Daim duab 1).Cov khoom siv hauv tsev neeg 3.3V no suav nrog 4-megabit, 2-megabit, 1-megabit, thiab 512-kilobit PROM uas muab txoj hauv kev yooj yim-touse, nqi-zoo rau reprogramming thiab khaws cia Xilinx FPGA configuration bitstreams.

Thaum FPGA nyob hauv Master Serial hom, nws tsim lub moos teeb tsa uas tsav lub PROM.Lub sijhawm luv luv tom qab CE thiab OE tau qhib, cov ntaub ntawv muaj nyob rau ntawm PROM DATA (D0) tus pin uas txuas nrog FPGA DIN tus pin.Cov ntaub ntawv tshiab muaj nyob rau lub sijhawm luv luv tom qab txhua lub moos nce.FPGA tsim cov naj npawb tsim nyog ntawm lub moos pulses kom tiav cov teeb tsa.Thaum FPGA nyob hauv Slave Serial hom, PROM thiab FPGA raug kaw los ntawm lub moos sab nraud.

Thaum FPGA nyob hauv Master Xaiv MAP hom, FPGA tsim lub moos teeb tsa uas tsav PROM.Thaum FPGA nyob rau hauv Slave Parallel lossis qhev Xaiv MAP hom, ib qho oscillator sab nraud tsim lub moos teeb tsa uas tsav lub PROM thiab FPGA.Tom qab CE thiab OE tau qhib, cov ntaub ntawv muaj nyob rau ntawm PROM's DATA (D0-D7) pins.Cov ntaub ntawv tshiab muaj nyob rau lub sijhawm luv luv tom qab txhua lub moos nce.Cov ntaub ntawv yog clocked rau hauv FPGA ntawm cov nram qab no nce ntug ntawm CCLK.Lub oscillator khiav dawb tuaj yeem siv rau hauv Slave Parallel lossis Slave Select MAP hom.

Ntau yam khoom siv tuaj yeem raug cuam tshuam los ntawm kev siv CEO tso tawm los tsav CE cov tswv yim ntawm cov cuab yeej hauv qab no.Lub moos inputs thiab DATA outputs ntawm tag nrho cov PROMs nyob rau hauv no saw yog interconnected.Tag nrho cov khoom siv tau sib xws thiab tuaj yeem ua tau nrog lwm tus neeg hauv tsev neeg lossis nrog XC17V00 ib zaug programmable serial PROM tsev neeg.


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